Non-Volatile memory cells using floating gates to control the conduction of current in a planar channel region is well known in the art. See for example U.S. Pat. No. 6,747,310, as the scale of integration increases, i.e. the geometry of the lithography for semiconductor processing decreases in size, the problem with a planar channel region is that the channel region becomes narrower. This reduces the current flow between the source and drain regions, requiring more sensitive sense amplifiers etc. to detect the state of the memory cell.
Because the problem of shrinking the lithography size thereby reducing the channel width affects all semiconductor devices, a Fin-FET type of structure has been proposed. In a Fin-FET type of structure, a fin shaped member of semiconductor material connects the source to the drain regions. The fin shaped member has a top surface and two side surfaces. Current from the source to the drain regions can then flow along the top surface as well as the two side surfaces. Thus, the width of the channel region is increased, thereby increasing the current flow. However, the width of the channel region is increased without sacrificing more semiconductor real estate by “folding” the channel region into two side surfaces, thereby reducing the “footprint” of the channel region. Non-volatile memory cells using such Fin-FETs have been disclosed. Some examples of prior art Fin-FET non-volatile memory structures include U.S. Pat. Nos. 7,423,310 and 7,410,913. However, heretofore, these prior art Fin-FET structures have disclosed using floating gate as a stack gate device, or using trapping material, or using SRO (silicon rich oxide) or using nanocrystal silicon to store charges.